head
splash


Download IDT'11 Program

This event provides a unique forum to discuss novel approaches in design, automation and test in the Middle East and Africa (MEA) region for researchers and practitioners in the areas of VLSI design, test and fault tolerance to come together to discuss new research ideas and present new research results. This event will provide the only VLSI Design & Test-specific meeting in the MEA region. Workshop topics include all aspects of design, test and automation. Specific topics are to include:

  • System Specification and Modelling
  • System Design Methods
  • SOC/NOC/MPSOC
  • Quantum MEMs
  • Architectures and Nanotechnology Architecture
  • Reconfigurable Computing
  • Emerging Technologies, Systems and Applications
  • Architectural and Logic synthesis
  • Design of Low Power Systems and Power Analysis
  • Packaging
  • Design Verification and Formal Methods
  • Mixed-Signal and RF Design
  • IC Physical Design Automation
  • Test Generation, Simulation and Diagnosis
  • Design For Test
  • Embedded Systems
  • Real Time Systems
  • Defect-Based Test
  • Fault Modeling
  • Test Issues in Nanotechnology
  • Built-In Self Test (BIST)
  • Design for Manufacturability (DFM)
  • Automatic Test Equipment
  • Analog and Mixed-Signal Test
  • On-Line Testing
  • Test Resource Partitioning
  • Failure Analysis
  • Fault Tolerance
  • Economics of Test
  • Applications Design: Media, Signal Processing, Wireless Communication and Networking, Automotive, Military, Secure Embedded Implementations, etc

PAPERS SUBMISSION

To present their work at the workshop, authors are invited to submit a full paper limited to six (6) pages in the standard IEEE conference double-column format, including figures and references. Each submission should include: title, full name and affiliation of all authors, an abstract of 150 words, and keywords. It should also identify a contact author and include a complete correspondence address, phone number, fax number, and E-mail address. All submissions must be made electronically in PDF format through IDT 2011 e-papers. Proposals for panels, hot topic sessions and embedded tutorials are also invited. Please ensure that your PDF file is readable by Acrobat Reader. The submission of a paper, a hot topic session or a panel proposal will be considered evidence that upon acceptance, the author(s) will present the paper or organize the panel at the workshop.

IMPORTANT DATES

Submission Deadline: 15 September 2011
Notification of Acceptance: 7 October 2011
Deadline for Paper Inclusion in Workshop Digest: 17 October 2011

IDT 2011 is sponsored by IEEE Circuits & Systems Society, and is technically co-sponsored by the IEEE Computer Society Test Technology Technical Council (TTTC)